1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices and, more particularly, to the manufacture of high performance submicron semiconductor devices and, even more particularly, to a method for the manufacture of high performance submicron semiconductor devices having ultrathin gate oxide structures in which anomalies on the interface surface between the gate oxide and the silicon substrate are negated.
2. Discussion of the Related Art
The semiconductor industry is characterized by the dual requirements of an increase in the speed of integrated circuits and an increase in the density of elements in integrated circuits. Thus, these two requirements have become the two major goals of MOSFET scaling. Increasing the density of elements means, primarily, that smaller channel lengths and widths are necessary. Increasing the speed of integrated circuits means, primarily, that the MOSFET saturation drain current I.sub.DSAT must be increased to allow faster charging and discharging of parasitic capacitances. Existing performance models for MOSFETs predicted that a decrease in either the channel length, L, or the gate oxide thickness, t.sub.ox, would increase I.sub.DSAT. However, as devices were scaled below approximately 2 .mu.m, "short-channel" effects were observed that were not predicted by the existing performance models which were then referred to as "long channel" models. For example, one of the short channel effects that was not predicted by the long channel model was that I.sub.DSAT becomes independent of channel length in extremely small MOSFETs and approaches a constant value regardless of any decrease in the channel length. It was also found that decreasing the gate oxide thickness, t.sub.ox, provided a much greater increase in I.sub.DSAT than a concomitant decrease in channel length, L. However, a thinner gate oxide thickness, t.sub.ox, will cause I.sub.DSAT to increase faster to the constant value as the channel length, L, is decreased. Therefore, decreasing the gate thickness, t.sub.ox, results in an increase in I.sub.DSAT in two ways and, therefore, it was determined that it is more advantageous to concentrate on methods to decrease gate oxide thickness rather than on methods to decrease channel length.
As device dimensions continued to decrease, it was determined that other short-channel effects needed to be addressed. All of the short-channel effects were placed into the following two general categories: (1) the problem of increased leakage current when the MOSFET is off and (2) the reliability problems associated with short-channel and thin gate oxide device structures.
The reliability problems that arise in short-channel and thin gate oxide MOSFETs include: (1) thin gate oxide breakdown; (2) device degradation due to hot-carrier effects; and (3) reliability problems associated with interconnects between MOSFETS. The problems that are of interest are the phenomena of thin gate oxide breakdown and the phenomena of device degradation due to defects or faults at the silicon substrate-gate oxide (Si--SiO.sub.2) interface.
The characteristics of the Si--SiO.sub.2 interface in a MOSFET determine, to a significant extent, the functioning of the gate dielectric. A study of the structure of the silicon substrate-gate oxide interface has resulted in the identification of various types of defects or faults that exist at the interface. FIG. 7 illustrates three types of anomalies that are typically found on the surface 700 of a silicon substrate 100. A first type of anomaly on the surface 700 is shown at 702 and represents a dislocation in the crystal structure of the silicon substrate 100. A second type of anomaly on the surface 700 is shown at 704 and represents a particle of a contaminant material on the surface 700. A third type of anomaly on the surface 700 is shown at 706 and is shown as a pit or cavity in the surface 700. The effects of these defects have become more apparent and more critical as the thickness of the gate oxide has been scaled concomitantly with the decrease of device dimensions into the submicron regime.